Verilog代码后，首现针对代码建模进行仿真，并考虑电路的实现因素，该仿真环节叫做 。

(1)8线-3线优先编码器的Verilog代码: module Encoder8to3_bh( input EI, input [7:0] I, output reg [2:0] Y, output reg GS, E0 ); always @ (EI, I) begin if(EI==0) begin Y=3'd0; GS=0; EO=0; end else begin GS=1; EO=0; casex(I) 8'b1xxx_xxxx: Y=3'd7; 8'b01xx_xxxx: Y=3'd6; 8'b001x_xxxx: Y=3'd5; 8'b0001_xxxx: Y=3'd4; 8'b0000_1xxx: Y=3'd3; 8'b0000_01xx: Y=3'd2; 8'b0000_001x: Y=3'd1; 8'b0000_0001: Y=3'd0; default: begin Y=3'd0; GS=0, EO=1; end endcase end end endmodule 2. 调用上述模块构成的16线-4线优先编码器 module Encoder16to4_bh( input EI1, input [15:0] A, output [3:0] L, output GS, EO0 ); wire EO1, EI0, GS1, GS0; wire [2:0] Y0, Y1; Encoder8to3_bh EU0(.EI(EI0), .I(A[7:0]), .Y(Y0), .GS(GS0), .EO(EO0)); Encoder8to3_bh EU1(.EI(EI1), .I(A[15:8]), .Y(Y1), .GS(GS1), .EO(EO1)); or G0(L[0], Y0[0], Y1[0]), G1(L[1], Y0[1], Y1[1]), G2(L[2], Y0[2], Y1[2]), G3(GS, GS1, GS0); assign EI0=EO1; assign L[3]=GS1; endmodule